Various types of circuitry are tested for jitter tolerance by exciting the circuitry with one or more jittered test signals and then measuring and analyzing the circuitry's response(s) to the jittered signal(s). One example of such jitter testing is the testing of serializer/deserializer (SerDes) devices to determine their bit error rate (BER), which is a key figure of merit for SerDes devices. A specific example of jitter testing is disclosed in U.S. patent application Ser. No. 10/838,846, entitled “System And Method For Testing Integrated Circuits,” filed on May 3, 2004, in the names of Roberts et al., that is incorporated by reference herein in its entirety.
FIG. 1 shows an exemplary prior art jitter generator 100 for stimulating circuitry 104 of a device-under-test (DUT) 108 with a full-test-speed jittered test signal 112 in a conventional manner. Conventionally, a low-frequency reference signal 116 is scaled up to a desired test frequency by a frequency scaler 120 so as to create a full-speed reference signal 124. A modulation signal 128 is then injected into full-speed reference signal 124 by injection circuitry 132 so as to create full-speed jittered test signal 112. Modulation signal 128 is sometimes an analog waveform generated using an arbitrary waveform generator. In the context of testing high-speed digital integrated circuits and systems, sometimes arbitrary signals are not required and only random noise tolerance is verified. In such a scenario, jitter injection can be simplified further by directly superimposing modulation signal 128 (in this case noise) onto full-speed reference signal 124. While this simplifies the implementation, it still requires an analog input from an arbitrary waveform generator or alternative noise source.
U.S. Pat. No. 6,665,808 discloses a state-of-the-art test signal generator that utilizes a microprocessor for generating a nominal parameter value signal and a memory for storing and generating a parameter variation value signal. The nominal parameter value signal and parameter variation value signal are combined by a coupler that provides the combined signal to a full-speed reference signal.
These schemes generally work well for relatively low- and moderate-frequency test signals. However, as circuitry speeds increase, jitter injection circuits become more and more difficult to implement due to their increasing sensitivity to disturbances, such as noise, environmental effects and parasitic effects, that affect the quality of the full-speed test signal. This difficulty is typically manifested as increased cost of implementation due to factors such as the need to use exotic semiconductor processing techniques and/or materials and/or relatively complex circuitry to implement conventional high-speed test signal generators. What is needed are a low-cost system and method for generating high-quality full-speed jittered signals for jitter testing.